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150 nm CMOS-12M Structured Array
Description
CMOS-12M is NEC Electronics’ new structured array technology with embedded high-density SRAMs and analog PLLs. The technology enables the integration of large size SRAM modules in structured array and is capable of supporting up to 2.6 Mb of embedded SRAM and up to 4 million raw gates. High system performance can be achieved with a system clock up to 200 MHz and a 333 MHz clock speed in local areas. The product offers a low unit price, low NRE and very short development and production times.
Features
- 150 nm technology according to ITRS (0.13 µm drawn, 0.11 effective gate length)
- Fine-grained structured ASIC technology, with prior embedded transistor grid
- Up to 6 metal layers, of which 5 are customizable
- Up to 4 millions raw gates
- Embedded blocks of pre-diffused dual-port SRAM, analog phase-locked loops (APLL), digital delay-locked loops (DLLs)
- Up to 200 MHz system frequency
- Core voltage 1.5 V with
optimized architecture
- Extremely low power dissipation
down to 20 nW/MHz/gate
- Flexible I/O structure supports LVTTL, PCI, PCI-X (mode1), LVDS, LVCMOS 2.5, SSTL2/3, HSTL, GTL+, LVPECL (input)
- Various package types: QFP, FPBGA, PBGA and ABGA
Product Outline
|
Feature
|
Description
|
|
Power supply
|
Core
|
|
1.5 V ± 10%
|
|
Interface
|
|
LVTTL; PCI; PCI-X (mode 1); LVDS; LVCMOS 2.5; SSTL 2/3; HSTL; GTL+; LVPECL
(input)
|
|
System frequency
|
200 MHz (333 MHz @ local)
|
|
Delay time
|
62 ps (2-input NAND, F/O = 1, typical length)
|
|
Power (VDD = 1.5 V)
|
20 nW/MHz/gate
|
|
Customizable metal layers
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5 ML/6 ML, aluminium
|
|
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SRAM
|
Small masters
|
32-bit x 512 word; 36 ps access time; dualport (1 RW + 1 RW)
|
|
Large masters
|
36-bit x 512 word; 146 ps access time; dualport (1 RW + 1 RW)
|
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APLL
|
Small masters
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1 or 2 phase shift type; 1 SSCG
|
|
Large masters
|
4 phase shift type
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|
DLL
|
Large masters
|
8 (100 to 175 MHz)
|
|
Package
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QFP (100-208); FPBGA (108-304); PBGA (256-676); ABGA (352-756)
|
|
Temperature ranges
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Ta = -40 to +85 °C; Tj = -40 to +125 °C
|
Master Line-up
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Small master
|
µPD66201
|
µPD66202
|
µPD66203
|
µPD66204
|
µPD66205
|
|
Density
|
Raw gates
[K gates]
|
250
|
603
|
729
|
1,242
|
2,030
|
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Usable gates
[K gates]
|
125
|
302
|
365
|
621
|
1,015
|
|
Embedded SRAM [Kbits]
|
96
|
208
|
320
|
432
|
576
|
|
I/O pads Note
|
180
|
276
|
324
|
404
|
500
|
|
Large master
|
µPD66206
|
µPD66207
|
µPD66208
|
µPD66209
|
µPD66210
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Density
|
Raw gates
[K gates]
|
2,000
|
2,400
|
2,400
|
3,000
|
4,000
|
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Usable gates
[K gates]
|
1,000
|
1,200
|
1,200
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1,500
|
2,000
|
|
Embedded SRAM [Kbits]
|
1,044
|
1,800
|
2,604
|
432
|
828
|
|
I/O pads*
|
596
|
708
|
812
|
596
|
708
|
* Includes power pins and GND
pins (the total available number of signal pins depends on the package type)
Package Line-up
| Package type |
Number of pins |
Edge length [mm] |
Pin/ball pitch |
| QFP |
100 |
14 |
0.5 |
| 144 |
20 |
0.5 |
| 208 |
28 |
0.5 |
| FPBGA |
108 |
11 |
0.8 |
| 160 |
13 |
0.8 |
| 208 |
15 |
0.8 |
| 304 |
19 |
0.8 |
| PBGA |
256 |
17 |
1 |
| 320 |
19 |
1 |
| 676 |
27 |
1 |
| ABGA |
352 |
35 |
1.27 |
| 500 |
40 |
1.27 |
| 576 |
40 |
1.27 |
| 672 |
45 |
1.27 |
| 756 |
45 |
1.27 |
|
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