 Instant Silicon Solution Platform
The new way to do high-performance ASIC design
| High performance |
You are used to get this with a cell-based design. |
| Easy to design |
You are used to get this with gate-arrays. |
| |
With ISSP you will get both! |
 NEC provides in this new field of structured ASICs with two processes ISSP1 with 150nm (ITRS technology node) (0.13µm drawn gate length) and ISSP90 with 90nm technology node (0.065µm drawn gate length). Further details can be found on the ISSP Technology page.
Finish designs in record time using best-in-class EDA tools certified by NEC
Electronics for ISSP with the special design
flow.
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