NEC Electronics Introduces “M2” 3.5G Mobile Handset LSI Chip with Advanced Low Power Consumption Technologies

NEC Electronics Corporation today introduced the M2 system LSI chip that integrates third generation (3G to 3.5G) W-CDMA and HSDPA communications technologies with application functions, with advanced low power technologies optimized for mobile handsets. The chip utilizes a 3.5G digital baseband (DBB) technology developed by Adcore-Tech, the mobile communications joint venture established in August 2006. The M2 chip is part of NEC Electronics’ Medity™ series of mobile handset solutions, and is the successor to the “M1” chip introduced in September 2006, renowned for its best-in-class 700-hour standby time. While the M1 was based on the ARM926EJ-S™ CPU core, the M2 chip utilizes the more advanced ARM1176JZF-S™ core, delivering a significant improvement in performance.

Through a combination of several advanced technologies, power consumption was reduced by 50 percent. This improvement was made possible by a host of advancements in circuit design and layout, including dynamic frequency scaling, automatic hierarchical clock control, LCD Direct Path technology, on-chip power switch technology, Quick Recovery technology. In addition, the use of 65-nanometer process technologies such as Multi-Vt transistor technology, and back-bias technique also contributed to lower power consumption. NEC Electronics also utilized LongRun2 technology licensed from Transmeta. These advancements in power consumption technology not only help to extend battery life and usage time, they also contribute to minimizing the size of the mobile handset battery itself, leading to flexibility in designing slimmer handsets, and also reducing environmental impact.The main technologies used in the M2 chip are as follows:

1. Reduction in active power consumption (design technology)
Dynamic frequency scaling technology reduces active power consumption by monitoring the bus traffic and automatically adjusting the system clock frequency. In addition, automatic hierarchical　clock control technology monitors the macros and automatically stops a clock when a macro is not active, further reducing active power consumption.

2. Reduction in LCD control  power consumption in system standby mode (design technology)
In standby mode, LCD Direct Path technology transfers data necessary for LCD display directly from the frame buffer to the LCD controller, bypassing the main bus, and thereby reducing standby power consumption.

3. Reduction in leakage current due to internalized power switches (design technology)
On-chip power switches help reduce leakage current when the macro is not active. In addition, a Quick Recovery technology helps save leakage current and makes it convenient to power off the CPU frequently. This is enabled automatically by hardware. The internal state of the CPU is saved before it is powered down. When an interrupt occurs, the technology restores the internal state of the CPU and power without rebooting.

4. Reduction in leakage current due to Multi-Vt transistors (design and process technologies)
By utilizing three different types of Vt transistors, the M2 chip is able to achieve both high-speed operation and low leakage current. The High-Vt transistors are low-speed but also have low leakage current, making it ideal for the DBB, which is always on. On the other hand, the Low-Vt transistors have higher leakage current but also high speed performance, achieving 500MHz operating performance optimal for the application CPU and DSP.

5. Reduction in leakage current due to back-bias technique (design and process technologies)
For the high speed CPU and DSP, which rely on low-Vt transistors, back-bias technique maintains optimal threshold voltage and helps reduce leakage current. CPU and DSP speed can be optimized while leakage current is reduced, without leakage variation, by monitoring the timing of the ring oscillator.

In addition to the improvements in power consumption, the M2 helps reduce total bill of materials (BOM) parts by reducing the number of external parts, by sharing the external memory used by the application processor and the DBB. M2 is also based on NEC Electronics’ platformOViA™ to facilitate efficient software development.

M1 and M2 are the backbone of NEC Electronics’ Medity solution suite that supports the features needed to develop the communications core of mobile handsets. Medity includes the following products and services:

(1) a chipset that includes a DBB and application processor, RFIC, and power IC

(2) software to drive the system LSI

(3) evaluation boards and reference design kits

(4) development tools for communications software and application software support, and

(5) system integration services to port fundamental software and middleware.

Medity2, which will be based on the M2 chip, is expected to be released at the end of 2007. With the introduction of M2 and the upcoming Medity2, NEC Electronics aims to maintain its leadership in the low power technologies, and continue its contributions to the mobile handset industry and beyond.

AvailabilitySamples of the M2 chip are available now. Volume production is scheduled to begin in October 2007, and reach approximately 1 million units per month by 2008. Availability is subject to change.

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ARM926EJ-S and ARM1176JZF-S are trademarks of ARM Ltd. Medity and platformOViA are trademarks of NEC Electronics Corporation. All other trademarks are the property of their respective owners.