Solution benefits when using gate array ASICs

Very low cost
Gate array ASICs are a very low-cost (ie. low unit cost AND low investment cost) technology. This is in particular true when quantities exceed a certain critical level, from which onwards investment cost are already amortized by the savings in unit cost. Depending on the level of complexity of a design, the critical quantity level from which onwards a gate array solution is commercially more attractive than a comparable field-programmable gate arrays (FPGA) solution can already be as low as 1,000 pieces per year.

Besides the purely commercial benefits, gate array ASIC solutions from NEC Electronics have by nature some very strong advantages over other solutions like SRAM-based field-programmable gate arrays.

Wide range operating ambient temperature / Ta
All gate array solutions offered by NEC Electronics feature a full ambient temperature range from -40 up to +85°C.

Single supply voltage
NEC Electronics' gate array solutions do only require a single supply voltage with an accuracy of only +/- 10% for proper operation.

High performance
Due to the fact that gate array solutions are using hard-wired connections for the logic imlpementation they are inherently faster than other solutions like FPGAs.

Low power consumption
Gate arrays show a much smaller power consumption in comparison to FPGAs for two reasons: Firstly, the hard-wired logic results in much smaller leakage currents and secondly, the rush current during the power-on phase is also significantly lower.

Small number of I/Os
For the same application, gate array ASICs do need significantly less I/O pins as other solutions. Firstly, no programming pins are required and secondly - due to smaller power consumption - less power and ground pins are needed. The reduction of I/O package pins usually comes along with the reduction of package size.

Fast start-up time
As gate array ASICs are hard-wired and do not need to be re-programmed after powering up, they are started-up much faster than FPGAs. Gate arrays do typically need only less than 1msec for starting-up.

Low failure rate
Gate array ASICs show a very low failure rate of typically less than 3 FIT. Again, due to their SRAM-based architecture, FPGAs feature much worse values here. So-called soft errors, where especially the FPGAs of the newest generations are extremely susceptible to, are unknown to gate array ASICs.

High design data security
The circuit data with the customer proprietary design details are protected by hard-wired connections within the gate array chip. As compared to FPGAs, there is no bit stream necessary from the outside for re-programming at every start-up.

Direct 5 Volt interface
With NEC Electronics gate arrays ASICs direct 5V connections are possible without any additional external components (e.g. resistors).

Wide choice of packaing solutions
NEC Electronics' gate array ASICs are available with a very wide choice of different packaging solutions, ranging from high-end Advanced BGA packages (ABGA) over all kinds of QFP packages to very small outline, low pin-count Tape Fine-Pitch BGA, SSOP or QFN packages.