SYSTEM-ON-CHIP LITE+

Customizable ARM7TDMI-S-based microcontroller, Ethernet-ready

System-on-Chip Lite+ stands for easy development of customized microcontrollers and SoC designs with Ethernet functionality. The basis of System-on-Chip Lite+ is a complete microcontroller subsystem consisting of an ARM7TDMI-S CPU core, a multi-port memory controller, a 10/100M Ethernet MAC and several peripherals. The single-chip System-on-Chip Lite+ device also contains a Gate Array area for user defined logic (UDL) that allows customers to freely implement proprietary and application-specific functions. These are the unique advantages of System-on-Chip Lite+ compared with discrete solutions:

• System-on-Chip Lite+ contains a complete microcontroller subsystem
• System-on-Chip Lite+ features peripherals and a bussystem architecture enabling high-data throughput
• System-on-Chip Lite+ features Ethernet connectivity
• System-on-Chip Lite+ can be freely extended by using the Gate Array area
• System-on-Chip Lite+ is based upon the well-established ARM7 CPU architecture

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System-on-Chip Lite+ solution advantages:

• Integrated one-chip device
• Optimization of data & signal flow
• In-system verification with dedicated development board
• PCB area & cost reduction
• Reduced power consumption
• Higher speed

The System-on-Chip Lite+ microcontroller subsystem is fully developed and pre-verified. This means the developer is freed from the task of producing a microcontroller subsystem from scratch. NEC Electronics has done the job for him, providing a system with ARM7TDMI-S CPU core, bus systems, interface controllers and peripheral controllers, adapted and connected via the applicable AMBA™ bus system, ie, AHB or APB. All the System-on-Chip Lite+ developer has to do is to connect the custom or application-specific function blocks in the UDL area to the microcontroller subsystem via the AMBA™ bus systems. The important part, however, of the System-on-Chip Lite+ microcontroller subsystem is the memory subsystem. The primary goal here is to achieve minimum latency for memory access in order to fully exploit the performance of the ARM7TDMI-S CPU core. On the ARM7TDMI-S side, there is a specified interface that also allows IP macro blocks from third-party suppliers to be integrated easily into the System-on-Chip Lite+ device.